Reliability Modeling of Circuits with Multi-State Aging Gates

As electronic devices are being scaled towards single digit nanometers, the frequency of errors that such nanocircuits will exhibit is expected to increase sharply. This is both a warning sign and a call to arms for including reliability/yield from the very early circuit design phases as a fourth optimization parameter (besides area, power and speed). In this paper we present an approach for reliability modeling of circuits, where every gate is considered as a discrete stochastic model. These models have (a few) discrete states, including an operating and a faulty state. This allows for treating the aging phenomena of circuits more realistically and obtaining more accurate reliability estimates.